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Published on Feb 11, 2016

Abstract

Microprocessor performance has improved rapidly these years. In contrast, memory latencies and bandwidths have improved little. The result is that the memory access time has been a bottleneck which limits the system performance.

Memory controller (MC) is designed and built to attacking this problem. The memory controller is the part of the system that, well, controls the memory. The memory controller is normally integrated into the system chipset.

This paper shows how to build an Advanced Micro controller Bus Architecture (AMBA) compliant MC as an Advanced High-performance Bus (AHB) slave.

The MC is designed for system memory control with the main memory consisting of SRAM and ROM. Additionally, the problems met in the design process are discussed and the solutions are given in the paper

LANGUAGE USED:

VHDL

TOOLS REQUIRED:

Simulation: ModelSim XE III 6.4b.

Synthesis: XiLinx ISE 10.1.