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Published on Feb 11, 2016

Abstract

The design of reversible networks has received much attention in recent years. The primary motivation of this work is huge power consumption in irreversible circuit. As observed, use of traditional (irreversible) logic gates results in information loss and causes inherent energy dissipation in a circuit, regardless of its realization.

A system is said to be reversible if it is information lossless.

The Galois field multiplier design is one of the most well-researched and widely investigated topics, having great impact on the solvability of large class of design problems in cryptography, coding theory, Galois switching theory and digital signal processing.

In the Galois field, there are two basic arithmetic operations: addition and multiplication. Over the years, many solutions have been proposed for efficient multiplier design, such as bit-serial, digit-serial and bit parallel. It is shown that an adder over GF(2) can be designed with m garbage bits and that of a PB multiplier with 2m garbage bits.

To tackle the problem of errors in computation, we also extend the circuit with error detection feature. Gate count and technology oriented cost metrics are used for evaluation. The expression for the upper bound for gate size is also derived for special primitive polynomials

Proposed System:

Error detection feature is incorporated into the design, using parity prediction technique

LANGUAGE USED:

VHDL

TOOLS REQUIRED:

Simulation: modelsim5.8c

Synthesis: Xilinx 9.1