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Published on Feb 11, 2016

Abstract

A new mapping scheme and its hardware implementation to error-freely compute the Daubechies 8-tap wavelet transform is presented. The multidimensional technique maps the irrational transform basis coefficients with integers and results in considerable reduction in hardware and power consumption.

When implemented in Xilinx FPGA, the scheme costs 518 logic cells, 186 registers and runs at a frequency of 71MHz.

While comparing with finite-precision architecture, the proposed scheme yields a reduction of 15% in hardware and 41% in power consumption for similar image reconstruction, and noticeable improvement in image reconstruction quality

LANGUAGE USED:

VHDL

TOOLS REQUIRED:

Simulation: ModelSim XE III 6.4b.

Synthesis: XiLinx ISE 10.1.