Abstract

The multilayer advanced high-performance bus (ML-AHB) busmtrix employs slave-side arbitration. Slave-side arbitration is different from master-side arbitration in terms of request and grant signals since, in the former, the master merely starts a burst transaction and waits for the slave response to proceed to the next transfer. Therefore, in the former, the unit of arbitration can be a transaction or a transfer. However, the ML-AHB busmatrix of ARM offers only transfer-based fixed-priority and round-robin arbitration schemes.

In this paper, the design a flexible arbiter for the ML-AHB busmatrix to support three priority policies—fixed priority, round robin, and dynamic priority—and three data multiplexing modes—transfer, transaction, and desired transfer length. In total, there are nine possible arbitration schemes. The proposed arbiter, which is self-motivated (SM), selects one of the nine possible arbitration schemes based upon the priority-level notifications and the desired transfer length from the masters so that arbitration leads to the maximum performance.

LANGUAGE USED:

VHDL

TOOLS REQUIRED:

• Simulation: modelsim5.8c
• Synthesis: Xilinx 9.1

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