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Published on Sep 16, 2019


The Discrete Wavelet Transform is a signal processing technique in which has found wide acceptance data compression. Considerable work has been done in designing systolic architecture to perform DWT.

This paper proposes systolic array architecture to compute 1-D discrete wavelet transform (DWT). The proposed systolic array consists of L processing elements (PE), where L denotes the number of levels. The main focus of this project is to achieve power reduction and reduction of Hardware complexity.

The fundamental idea behind wavelets is to analyse according to scale. Indeed, some researchers in the wavelet field feel that, by using wavelets, one is adopting a whole new mindset or perspective in processing data. Wavelets are functions that satisfy certain mathematical requirements and are used in representing data or other functions, this idea is not new.

Approximation using superposition of functions has existed since the early 1800's, when Joseph Fourier discovered that he could superpose sines and cosines to represent other functions. However, in wavelet analysis, the scale that we use to look at data plays a special role. Wavelet algorithms process data at different scales or resolutions.

If we look at a signal with a "large window", we would notice gross features. Similarly, if we look at a signal with a "small window", we would notice small features. The result in wavelet analysis is to see both the forest and the trees, so to speak.

This makes wavelets interesting and useful. For many decades, scientists have wanted more appropriate functions than the sine's and cosines, which comprise the bases of Fourier analysis, to approximate choppy signals.

By their definition, these functions are non-local (And stretch out to infinity). They therefore do a very poor job in approximating sharp spikes. But with wavelet analysis, we can use approximating functions that are contained neatly in infinite domains. Wavelets are well suited for approximating data with sharp discontinuities.




Simulation: modelsim5.8c

Synthesis: Xilinx 9.1

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