Synchronous DRAM (SDRAM) has become a mainstream memory of choice in design due to its speed, burst access and pipeline features. For high-end applications using processors, the interface to the SDRAM is supported by the processor's built-in peripheral module.
However, for other applications, the system designer must design a controller to provide proper commands for SDRAM initialization, read/write accesses and memory refresh.
This SDRAM controller reference design, located between the SDRAM and the bus master, reduces the user's effort to deal with the SDRAM command interface by providing a simple generic system interface to the bus master.
The basic blocks in the SDRAM controller consists of three modules: the main control module, the signal generation module and the data path module.
The main control module, containing two state machines and a counter, is the primary module of the design which generates proper i-State and c-State outputs according to the system interface control signals.
The signal generation module generates the address and command signals required for SDRAM based on i-State and c-State. The data path module performs the data latching and dispatching of the data between the bus master and SDRAM.
This Simplifies SDRAM command interface to standard system read/write interface. The internal state machine built for SDRAM to power-on initialization and Read/write cycle access time is getting optimized automatically according to the SDRAM timing spec and the mode it's configured to. This provides dedicated auto-refresh requests input and acknowledge output for SDRAM refresh and it is easily configurable to support different CAS latency and burst length
Synthesis: Xilinx 9.1