In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic unit(s), but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar.
Although adders can be constructed for many numerical representations, such as Binary-coded decimal or excess-3, the most common adders operate on binary numbers. In cases where two's complement or one's complement is being used to represent negative numbers, it is trivial to modify an adder into an adder-subtractor.
Other signed number representations require a more complex adder.The adders that will come under Simple Adders are Half Adder and Full Adder and the adders that will come under Complex Adders are Ripple Carry Adder , Carry Look Ahead Adder and so on. By combining multiple carry look-ahead adders even larger adders can be created which are known as Look – ahead Carry unit. This can be used at multiple levels to make even larger adders.
Carry Select Adder (CSA) is known to be the fastest adder among the conventional adder structures. It is used in many data processing units for realizing faster arithmetic operations. In this paper, we present an innovative CSA architecture. It employs a novel incrementer circuit in the interim stages of the CSA.
The main advantage of CSA is its reduced propagation delay characteristics. This is realized by the use of parallel stages that results from multiple pairs of ripple carry adder
Simulation: ModelSim XE III 6.4b.
Synthesis: XiLinx ISE 10.1.