This paper proposes an improved version of lifting based 3D Discrete Wavelet Transform (DWT) VLSI architecture which uses bi-orthogonal 9/7 filter processing. The whole architecture was optimized in efficient pipeline and parallel design way to speed up and achieve higher hardware utilization.
The Discrete Wavelet Transform (DWT) was based on time-scale representation, which provides efficient multi-resolution.
The lifting based DWT architecture has the advantage of lower computational complexities transforming signals with extension and regular data flow. This is suitable for VLSI implementation. It uses a cascade combination of three 1-D wavelet transform along with a set of in-chip memory buffers between the stages.
The discrete wavelet transform (DWT) is being increasingly used for image coding. This is due to the fact that DWT supports features like progressive image transmission (by quality, by resolution), ease of compressed image manipulation, region of interest coding, etc.
DWT has traditionally been implemented by convolution. Such an implementation demands both a large number of computations and a large storage features that are not desirable for either high-speed or low-power applications.
Recently, a lifting-based scheme that often requires far fewer computations has been proposed for the DWT. The main feature of the lifting based DWT scheme is to break up the high pass and low pass filters into a sequence of upper and lower triangular matrices and convert the filter implementation into banded matrix multiplications.
Such a scheme has several advantages, including "in-place" computation of the DWT, integer-to-integer wavelet transform (IWT), symmetric forward and inverse transform, etc. Therefore, it comes as no surprise that lifting has been chosen in the upcoming
Simulation: ModelSim XE III 6.4b.
Synthesis: XiLinx ISE 10.1.